1. Field of the Invention
The invention relates in general to a method for fabricating of semiconductor integrated circuits (ICs). and more particularly to a method for fabricating a capacitor.
2. Description of the Related Art
DRAM is a volatile memory, and the way to store digital signals is decided by charge or discharge of the capacitor in the DRAM. Therefore, when the power applied on the DRAM is turned off, the data stored in the memory cell completely disappears. One DRAM cell includes one field effect transistor (FET) and one capacitor. The capacitor is used to store the signals in the DRAM cell. If more charges can be stored in the capacitor, the capacitor has less interference when the data is sensed by the amplifier.
Mixed mode circuits in a semiconductor chip contain capacitors. At present, most capacitors are of the double-polysilicon capacitor (DPC) type as shown in FIG. 1. As shown in FIG. 1, a double-polysilicon capacitor 100 is a capacitor having an upper electrode 104 and a lower electrode 102, both fabricated from polysilicon material. There is a dielectric layer 106 between the upper electrode 104 and the lower electrode 102. N-type impurities, for example, can be doped into the polysilicon layer to increase its electrical conductivity. In general, the lower electrode 102 of the double-polysilicon capacitor 100 is connected to a ground terminal while the upper electrode 104 is connected to a negative bias voltage V.sub.bias. Hence, when the capacitor 100 is being charged, holes within the polysilicon lower electrode 102 migrate to a region on the upper surface of the lower electrode due to the negative bias voltage V.sub.bias. These holes compensate for the N-type impurities originally doped inside the polysilicon electrode 102. Consequently, a depletion region 108 is formed on the upper surface of the electrode 102, thus forming an additional dielectric layer. In other words, an additional dielectric layer is formed over the original dielectric layer 106, thereby thickening the overall dielectric layer and reducing the charge storage capacity of the capacitor. Furthermore, capacitance of the capacitor is unstable due to some minor fluctuation of the negative bias voltage V.sub.bias too.
In prior art, metal capacitors, which can prevent a depletion region from forming in a double-poly capacitor, are provided. One of the metal capacitors uses interconnect metal layers as an upper electrode and a lower electrode and uses an inter-metal dielectric layer as the dielectric film for a capacitor. Interconnect metal, inter-metal dielectric and interconnect metal constitute a similar capacitor structure, which is used as a parasitic metal capacitor. However, when the inter-metal dielectric layer is used to isolate two metal layers so that the inter-metal dielectric layer is thick, the dielectric film of a capacitor is thicker and the capacitance is less. The capacitance of the parasitic metal capacitor with a thick inter-metal dielectric layer is thus limited. If the parasitic metal capacitor requires a capacitance the same as that of a conventional capacitor, the parasitic metal capacitor needs a large area because the capacitance increases according to the dielectric area.